1. Field of the Invention
This invention relates to amplifiers and more particularly decreasing the power consumption of CMOS amplifiers.
2. Description of the Prior Art
CMOS circuitry is generally used where lower power consumption is desired such as in battery operated electronic components. However, the output stage of CMOS analog amplifiers are relatively inefficient.
These inefficiencies can be demonstrated by reference to FIG. 1, which is a typical two stage CMOS amplifier 10. The input stage 12 comprises differentially coupled P channel transistors MP1 and MP2 having their sources coupled to a current source, 11. The output is taken through an active load MN2 at the drain of one of the input transistors MP2 and coupled to drive the output stage.
The output stage 14 comprises a P channel transistor MP3 and an N channel transistor MN3, coupled in a source/sink configuration, compensation capacitor Cc and current source 12. Of all the components provided for in the output stage 14, only transistor MN3 is driven by the input stage 12. Hence, output stage source transistor MP4 must always be conducting a large amount of current. That current is determined by a current source 12. For the output stage to provide wide voltage swings and for the output to be able to source or sink relatively large amounts of current, the current through transistor MP4 must be large. However, when the input signal is quiescent, transistor MP4 will conduct the same current that it will conduct when the load is sinking a large amount of current. Further, it should be noted that in this implementation of an amplifier 10, transistor MP4 does not switch, irrespective of the input signal. Thus transistor MP4 is inefficient.
There have been a number of articles describing attempts to lower the power consumption of the output stage of CMOS amplifiers. These include J. A. Fisher, "A High Performance CMOS Power Amplifier", Institute of Electrical and Electronic Engineers (IEEE) Journal of Solid State Circuits (JSSC) Vol. SC-20, December, 1985; S. L. Wong and C. A. T. Salama, "An Efficient CMOS Buffer for Driving Large Capacitive Loads", IEEE JSSC vol. SC-21, June 1986; and F. N. L. Op't Eynde, P. F. M. Ampe, L. Verdeyen and W. M. C. Sansen, "A CMOS Large-Swing Low Distortion Three Stage Class AB Power Amplifier, IEEE JSSC vol. SC-25 February, 1990. Although these articles propose circuits that, with various degrees of success, provide a methodology for reducing power consumption, they generally increase the complexity of the circuit, require more transistors and thereby require a larger die size. Improved efficiency for the output stage typically results in distortion, and increased circuit complexity often creates noise.